With the high-speed communications system board design complexity increasing, dependence on any one particular CAD tools have been unable to complete the entire design and simulation within an acceptable range of accuracy. PCB designers and signal integrity (SI) design engineers need to adopt a variety of simulation tools. In addition to the main criterion of price, performance, speed and accuracy are always selection tool set, how to use CAD software tools from multiple EDA tool vendors to achieve design goals, SI and electromagnetic interference (EMI) design rules, but also Chinese design important issues of concern engineers. Generally a combination of good design and SI / EMI analysis tools should include: layout tools, board-level simulation, a field solver precise and detailed simulation engine.
The tool discussed in this paper include: allegro and SpecctraQuest, Hspice, Spicelink and HFSS:
Allegro is the general layout design tools; the same with the Allegro database, SpecctraQuest is used as the main tool for board-level simulation, avoiding the problems of data conversion;
Hspice is more accurate analysis tools;
Spicelink and HFSS provide 2D and 3D field solutions for a variety of interconnect geometries were analyzed (through holes, connectors, etc.), especially when the need for high frequency analysis.
In order to effectively utilize existing CAD tools, to use the appropriate tools at the right design stage. In this paper, between the card and the motherboard to 12.5Gbps transfer rate of 2.5Gbps high-speed communication system as an example, describes how to use a variety of simulation tools to solve Gbps speed PCB design issues.
Establishing design rules with SpecctraQuest
Allegro is layout tool, SpecctraQuest board-level simulation tool, a combination of both the advantage of sharing the same large database using the same simulation engine and similar graphical user interface. Due to the further integration of Allegro and SpecctraQuest, design engineers can simultaneously perform layout and simulation at the design stage. To make the design of the card and backplane can transmit 2.5Gbps, edge-rate serial data signal 100ps-200ps, we must grasp the SI issue in this band and to effectively manage. SI major issues that need to know include: skin effect, dielectric loss, coupling and drive pre-emphasis and so on. SpecctraQuest and simulation tools can address the following issues:
a. SignalExplorer use tool to extract pre-layout analysis and an important node. With the increasing complexity of the board, pre-layout analysis and design rules set increasingly important. SpecctraQuest circuit diagram using extraction tools, SignalExplorer The circuit parameters can be pre-layout analysis, and the ability to extract the important network node to which circuit browser, so late in the design and layout of the wiring checked. And many other circuit-level simulation tool, one drawback is the lack of detailed SpecctraQuest modeling capabilities, in other words, IBIS model is the only model of the device can be employed. Therefore, prior to analysis in SignalExplorer must reliably evaluate the behavior of the model. Using SignalExplorer can address the following issues: evaluation board hierarchical geometry, estimated skin effect and dielectric loss due to give high-speed data / clock permissible line length design rules, giving control of the coupling line spacing is given terminal type and maximum length mismatch values and all of the differential pair. Experience has shown that the design rules obtained from the above simulation can provide valuable guidance for engineering layout and wiring, thus greatly shortening design cycles and reduce design risk.
The equalization circuit. And because most of the devices have built-equalization circuit, IBIS class model it is difficult to compensate. By passive components separated from the device out into the circuit board, we can simulate the effect of the equalizer. SpecctraQuest use the modified netlist analysis, general guidelines can be applied to get the equalizer. When little effect on the medium, the equalizer should not play a role. The role of the equalizer is to compensate the loss of high frequency components of the long interconnection line. Pre-emphasis may result in shorter interconnect eye deteriorated. With the growth of the interconnect dielectric loss FR4 plate will increase. High frequency components of the signal (corresponding to a steep rising / falling edge) will disappear, the low frequency components were retained. In order to effectively use the pre-emphasis function, you must first estimate the length of the signal transmission path interconnect, and then decide whether to take compensatory measures. All high speed transmission interconnects have taken pre-emphasis is not optimal. Table 1 compares the signal through 2.5Gbps differential interconnect different length, the difference in the elements pre-emphasis at the on / off state of two kinds of eye diagram and jitter window b. The Loss and compensation of skin effect and dielectric loss is generally considered to be the main problem gigabit data transmission board design face. Skin effect determines the line width, dielectric loss depends on the material of the PCB. To solve these two fundamental issues, board-level simulation must have the ability to deal with lossy transmission line having a frequency of independent parameters, SpecctraQuest to meet this requirement. Simulation and measurement results show that the loss in the GHz band dominates the media. In communication systems, high speed data transfer to go through a long wire, which is easy to be affected by the dielectric loss and distorted. One way to overcome this loss of influence is the use of pre-emphasis and equalizer. There are several ways to choose a balanced, we only discuss the use of passive
Coupled c. GHz band at data rates below Gbps when the coupling has been a major factor in the effect of noise in PCB design metrics. Due to the higher frequency components of the signal coupling ratio of the signal frequency component of the invasion, so its loss than the original Gbps signal is subjected to a large loss, the impact on the natural noise indicators reduced. Most layout tools based on the coupling coefficient by the geometry and material routing decisions to estimate the impact of the coupling, which is derived linear estimation formula of parallel distance limit, which reduces the wiring density. In fact, in the long wiring coupling will reach saturation. In the estimation process to ignore the saturation effect will export more dense than necessary wiring design rules. To this end, the use of SpecctraQuest comprehensive simulation to determine the design of the coupling rules. For 2.5Gbps data, the rise time of 150PS typical value is, the length is about 300mil saturated, that is, the actual coupling line may be longer without increasing the coupling 300mil budget values. Table 2 shows the rate of 2.5Gbps, swing 500mv, a rise time of coupling parameters and saturation signal loss of 110ps. Coupled saturated at about 300-400mil place, because the magnitude of the loss so that a larger attenuation over long wiring. According to this law, design engineers can more efficiently routing, design rule that gives more than many layout tools more effectively
With Maxwell 2D / 3D design complex wiring structure
The transmission rate 10G to a higher rate of 12.5Gpbs, FR-4 sheet will have a great loss, better to use other loss characteristics plate. Shown in Figure 1 as a coplanar arrangement of the circuit board, which is used in the top of the board to 12.5Gbps data transmission of 10Gbps, the use of plates of RO4350. Low dielectric loss of the sheet, but only at the top / bottom of the wiring, which use surface transport 10GHz signal line. Coplanar structure signal quality is better, EMI is relatively low. To use 3D field solver tool calculates the line width and spacing to ensure that the line impedance of 50 ohms, so that the driver output impedance matching circuit. You can use Maxwell 3D field solver.
When the signal Gbps data rate transmission, through holes, connectors and associated thread can cause signal integrity problems, accurate modeling and simulation of connectors and through-hole effect for predicting signal quality is very important. VHDM and HSD model Maxwell 3D solver tool for extracting the connector, the connector after model, to be embedded in SpecctraQuest DML format for Hspice sub-circuit board-level simulation. In general, even if successful designed Gbps rate card, to design transfer rate 5-10Gbps backplane will still face many challenges. Maxwell field solver tool helps to create a connection model to achieve such data rates.
Detailed analysis using Hspice
a. use Hspice for power layer analysis GHz band, the power delivery is facing new challenges to using sophisticated modeling techniques and analytical tools to obtain the true (power) flat response. Hspice is able to achieve a precise sweep analysis tools, and an IC transistor model based on the interest for simultaneous switching noise (SSN) simulation. For the transfer layer to the high-frequency power supply differential element, you can use the transmission line mesh model to evaluate the behavior of high-frequency power / ground plane. For example, to analyze PCB a pair of 2 inches × 2.5 inches power / ground plane, the plane interval 3.5mil, requires edge rates 70ps, the bandwidth of 5GHz. The general practice is based on a key parameter index differential element, a target impedance differential budget each power / ground plane pair is 272m, the transmission line mesh model used to determine the frequency response of the power ground plane. For more than 1Gbps rate, it is recommended to be considered separately lossy and lossless case to determine the added dielectric loss of influence in the model. The model used for Hspice simulation, the resonance frequency of 1.2GHz, the simulation results show that: by the power / ground plane consider dielectric loss problem, can greatly reduce the resonance amplitude, frequency domain helps power / ground plane in response to to achieve target impedance requirements. Since the majority of high-speed serial data are based on the differential transmission mode, the power / ground plane dedicated 2.5Gbps differential signal transmission in. Ideally, due to the differential element having a differential characteristic rather than absorb transient current. Therefore, in practice the target impedance can be higher, by reducing unnecessary PCB layers, and also avoid super-index requirements for the design.
b. use Hspice evaluating components and high frequency analysis Although IBIS models are widely used for board-level simulation, a new element in the assessment, based on the transistor driver / receiver model analysis remains essential. With IC manufacturers increasingly in Hspice encrypted form based on the model of the transistor, Hspice emerged as the only tool element evaluation. Such simulations should include loading / unloading the package effect as well as different types of transmission lines and drive the length of the device. This requires manufacturers to provide the correct model and modify the model according to the actual element. After determining the elements, you can create and validate IBIS model according to the final Hspice model and function indicators. In the higher signal rates such 10-12.5Gbps, behavioral models are no longer valid for the device to work in the band, trying to create IBIS model does not make sense.
Simulation tools integration process
According to the research and SI design guidelines, we successfully designed to send and receive rates of up to 12.5Gbps circuit board, the board transfer rate of 2.5Gbps to 40Gbps data devices. As already discussed in detail how to use CAD tools to solve different design problems, however, a matter of design engineers often overlooked is: in high-speed design process, the face of many EDA tools when the selection of the tool?
Therefore, the design process should follow standard procedures to integrate simulation tools:
SI using Hspice and SpecctraQuest development model;
Using Maxwell and SpecctraQuest development boards layering strategy, parameters, and wiring layers model;
Hspice using decoupling capacitors on the supply plane analysis;
SpecctraQuest use low-level planning, layout indicators to determine, after the pre-wiring and wiring verification analysis.
In order to efficiently execute this process, the hardware design engineers and project managers must master the basics of SI and EMI
Currently, EDA tools in the field, in addition to a dedicated signal integrity design tools for special products, integrated tools to meet the urgent demand for high-speed PCB design industry for EDA tools enhance the design industry has become an important technology trends. This is reflected in the following aspects:
High-speed design borders has been extended from the previous communications products to mobile phones, digital imaging products like consumer electronics.
EDA tool vendors gradually recognized tools they offer faster solutions must be able to solve more complex design problems, we must be highly integrated to address the full range of PCB design challenges facing the industry, reducing complex high-speed circuit board design cycle
With high-speed devices, connectors, integrated circuit applications increasing, integrate multiple modeling languages PCB Signal Integrity design tool there is a big demand. Mentor Graphics company ICX 3.0 is an optional program, which supports SPICE, IBIS and VHDL-AMS's PCB signal integrity simulation tools in a single environment to avoid different types of models, using a variety of different sources of EDA tools set to bring development cycle delayed problems. As more and more high-speed PCB use of complex IC package, since the PCB and IC contains multiple, arbitrary shape of the power / ground layer, any number of vias and bounce the signal line, noise, power / ground layer, resonances, reflections and coupling problem wire segment and power / ground layers will be more serious, PCB design is inevitable to consider factors IC package, and how to generate frequency domain and time domain model PCB and IC for system-level simulation It is also an important issue facing the industry. Within an EDA tool integration of the full-wave analysis engine to perform quantization and processing board-level model by board-level electromagnetic field analysis features.