This design provides a good path for the signal current and its loop current. The proper routing strategy is that the first layer is traced along the X direction, the third layer is traced along the Y direction, the fourth layer is traced along the X direction, and so on. Intuitive to see the line, the first layer 1 and the third layer is a pair of hierarchical combination, the fourth and seventh layer is a pair of layered combination, 8th and 10th layer is the last pair of layered combination. When the direction of the alignment needs to be changed, the signal lines on layer 1 should be changed by "via" to layer 3. In fact, it may not always be done, but as a design concept or to try to comply.
Similarly, when the signal alignment direction changes, it should be through the hole from the 8th and 10th layers or from the 4th to 7th floor. This wiring ensures that the coupling between the forward path and the loop of the signal is tightest. For example, if the signal is routed on layer 1 and the loop is on layer 2 and only on layer 2, the signal on layer 1 is transferred to layer 3 even by "vias" The loop is still on the second floor, thus maintaining low inductance, large capacitance characteristics and good electromagnetic shielding performance.
If the actual alignment is not the case, how do? Such as the first layer of the signal line through the hole to the 10th layer, then the loop signal had to find from the 9th floor ground plane, loop current to find the nearest ground vias (such as resistors or capacitors and other components of the ground pin) The If you happen to have such a hole in the vicinity, it is really lucky. If there is no such vias available, the inductance will become larger, the capacitance will be reduced, EMI will increase.
When the signal line must pass through the hole from the current pair of wiring layer to the other wiring layer, should be placed near the hole in the ground through the hole, so that the circuit signal can be successfully returned to the appropriate ground plane. For Layer 4 and Layer 7 hierarchical combinations, the signal loop will return from the power plane or ground plane (ie, layer 5 or layer 6) because the capacitive coupling between the power and ground layers is good and the signal is easy to transmit The
Multi-power layer design
If the two power supply layers of the same voltage source need to output high current, the circuit board should be fabricated into two power supply layers and ground plane. In this case, an insulating layer is placed between each pair of the power supply layer and the ground layer. This gives us the desired equalization of the current of two pairs of impedance equal to the power bus. If the stacking of the power supply layer causes the impedance to be unequal, the shunt is not uniform, the transient voltage will be much larger, and the EMI will increase dramatically.
If there are multiple values of different supply voltages on the board, multiple power planes are required accordingly, keeping in mind the different power supply layers and ground layers for different power sources. In both cases, make sure that the pairing power supply layer and the ground plane are at the location of the circuit board, bearing in mind the manufacturer's requirements for the balanced structure.
to sum up
The discussion of circuit board delamination and stacking is limited to the fact that most engineers design circuit boards with a conventional printed circuit board with a thickness of 62 mil, without blind holes or buried vias. Thickness difference is too large for the circuit board, the proposed stratification scheme may not be ideal. In addition, with the blind hole or buried hole circuit board processing process is different from the stratification method is not applicable.
The thickness of the circuit board design, the via process and the number of layers of the circuit board is not the key to solve the problem. The excellent layered stack is to ensure the bypass and decoupling of the power supply bus so that the transient voltage on the power supply layer or ground layer is the smallest And the signal and power of the electromagnetic field shielding the key. Ideally, there should be an insulation barrier between the signal trace layer and its return ground layer, and the paired layer spacing (or one or more) should be as small as possible. According to these basic concepts and principles, can be designed to meet the design requirements of the circuit board. Now, IC's rise time is very short and will be shorter, this article discusses the technology to solve the EMI shielding problem is essential.