There are many ways to solve the EMI problem, modern EMI suppression methods include: the use of EMI suppression coating, select the appropriate EMI suppression parts and EMI simulation design. This paper discusses the role and design techniques of PCB layered stacking in controlling EMI radiation from the most basic PCB layout.
In the IC power supply pin near the appropriate placement of the appropriate capacity of the capacitor, IC output voltage can jump faster. However, the problem is not so far. Since the capacitor has a characteristic of limited frequency response, this makes it impossible to generate the harmonic power required to drive the IC output in a full frequency band. In addition, the transient voltage formed on the power supply bus creates a voltage drop across the inductor at both ends of the decoupling path. These transient voltages are the main common mode EMI sources. How should we solve these problems?
For the ICs on our circuit boards, the power supply layer around the IC can be seen as an excellent high-frequency capacitor that collects the amount of energy that is leaking from discrete capacitors that provide high-frequency energy for clean output. In addition, the excellent power supply layer inductance is small, so the inductance of the synthesis of the transient signal is also small, thereby reducing the common mode EMI.
Of course, the connection between the power supply layer and the IC power supply pin must be as short as possible because the rising edge of the digital signal is faster and faster, and it is best to connect directly to the pad where the IC power supply pin is located.
In order to control the common mode EMI, the power plane will help decouple and have a sufficiently low inductance, which must be a well-designed power layer pairing. Some people may ask, to what extent is it good? The answer to the problem depends on the stratification of the power supply, the material between the layers, and the operating frequency (ie, the function of IC rise time). Typically, the spacing of the power supply is 6 mils, the interlayer is FR4 material, the equivalent capacitance per square inch of the power supply layer is about 75pF. Obviously, the smaller the interlayer spacing, the larger the capacitance.
There are not many devices with a rise time of 100 to 300 ps, but devices with high rise times in the range of 100 to 300ps will have a high percentage according to the current IC development speed. For circuits with a rise time of 100 to 300 ps, the 3 mil layer spacing will no longer apply to most applications. At that time, it is necessary to use layer spacing of less than 1mil layered technology, and with a high dielectric constant material instead of FR4 dielectric material. Now, ceramic and pottery plastic can meet the design requirements of the 100 to 300ps rise time circuit.
Although new materials and new methods may be used in the future, for today's common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacings and FR4 dielectric materials are usually sufficient to handle high-end harmonics and make the transient signal low enough Said that the common mode EMI can drop very low. The PCB stacking design example presented in this paper will assume a layer spacing of 3 to 6 mils.
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