Analysis and Solution of Three Kinds of Interruption of ARM Single Chip Microcomputer

- May 05, 2017-

Analysis and Solution of Three Kinds of Interruption of ARM Single Chip Microcomputer

ARM microcontroller is the entry point for most novice selections, but because of the lack of knowledge, in the design process novice often encounter this or that problem, ARM abnormal interrupt return is such a headache. In the ARM use of the problem of abnormal interrupt return is a novice more distressing problem, this article will be on the ARM abnormal interrupt summary of the situation, and gives some solutions.

 

Before the formal introduction, we must add some of the more important basic knowledge. First, R15 (PC) always points to instructions that are "fetching" rather than instructions that are "executing" or "decode" instructions. In general, people habitually agree that "the instruction being executed as a reference point" is called the current first instruction, so the PC always points to the third instruction. When the ARM state, each instruction is 4 bytes long, so the PC always points to the address of the command plus 8 bytes of the address, that is: PC value = the current program execution position +8; and ADS pc is to debug to see Convenient and modified, it is pointing to the implementation of the instructions, that is, "real pc-8"!

 

SWI and undefined instruction exception interrupt return

 

Instruction Address:

 

A PC-8 The current instruction is SWI or undefined instruction, and the interrupt has occurred. The value of PC is not updated.

 

A + 4 PC-4 interrupts the processor to save PC-4 to LR. ; R!

 

A + 8 PC

(PC-4) from the next instruction A + 4 (PC-4) of the interrupt instruction A (PC-8), the value of LR is assigned to the PC directly. The specific instruction is MOV PC, LR ( PC = A + 4 = LR).

 

(A + 8); lr = pc - 4 (at this time the processor to determine, can not be the same time, the processor is not the same, for the SWI and undefined instructions are abnormal when the pc is not updated, according to ARM's three-tier pipeline principle, pc is not updated, Change!) That is A + 4.

 

Since this type of exception should be returned after the implementation of the next instruction (A +4), so return, pc = lr can.

 

IRQ and FIQ exception interrupt processing return address corresponding to PC A, PC-8 after the completion of this instruction is completed (!) Query IRQ and FIQ, if there is an interrupt request to generate an interrupt.

 

A + 4 PC-4

 

A + 8 PC; lr!

 

(At this point the value of the PC has been updated, pointing to A + 12. will the current PC-4, that is, A +8).

 

Save to LR. When returning, execute the instruction at A + 4 (LR-4), so the return instruction is:

 

SUBS PC, LR, # 4 (PC = A + 4 = LR-4)

 

Vernacular explanation: For general interrupt and fast interrupt exception, the interrupt must be detected after the completion of an instruction, such as the implementation of the instruction A is interrupted, such as the implementation of a command is not interrupted, the exception occurs (A + 12); lr = pc- 4 (at this time the processor can not change!) That is A +8 return, should be interrupted without the implementation of the instructions (above A +4) So when the return, pc = lr-4.

 

Instruction Prefetch Abort the exception interrupt processing

 

Instruction Address:

A PC-8 interrupt is executed when this instruction is executed. A + 4 PC-4 processor saves A + 4 (PC-4) to:

 

LR; lr! A + 8 PC

 

(PC-8) where instruction fetch is aborted, the return instruction is SUBS PC, LR, # 4 (PC = A = LR-4).

 

Vernacular explanation: for the prefetch instruction to stop the exception occurs prefetch instruction exception, is the implementation of the exception occurred, pc is not updated, that is pc = A +8; lr = pc - 4 (then the processor decided, can not change !) That is A + 4.

 

Since such an exception should be returned after the exception of the instruction (A), so return, pc = lr-4.

 

Data access aborts the return of exception interrupt handling

 

Instruction Address:

 

A PC-8 This instruction accesses the problematic data, and when the interrupt is generated, the PC value has been updated.

 

A + 4 PC-4 interrupt occurs when PC = A + 12, the processor saves A + 8 (PC-4) to LR.

 

A + 8 PC; lr!

 

(PC = A = LR-8), the instruction is SUBS PC, LR, # 8 (PC = A = LR-8)

 

Vernacular Explanation: For data access to abort an exception, it is a data error during execution.

(PC = A = LR-8), the instruction is SUBS PC, LR, # 8 (PC = A = LR-8)

 

Vernacular Explanation: For data access to abort an exception, it is a data error during execution.

 

Resulting in the exception, pc has been updated, that is pc = A +12.

 

Lr = pc-4 (then the processor determines, can not change!) That is A +8.

 

Since this exception is returned after the exception should be re-executed instruction (A), so return, pc = lr-8.

 

to sum up

 

Cause PC update is a reason for the suspension of data, there is interrupted.

 

The interrupt must be detected after an instruction has been executed, so it is only one that has not yet been executed. Instruction (pc-8), so pc = lr - 4;

 

As with interrupts, SWI and undefined instruction exceptions are also returned to the next instruction (pc-4), but they are not updated when they are executed, so pc = lr.

 

Prefetch instructions to stop the exception, there is no pc update, but it had to re-execute the exception that instruction, so pc = lr-4.

 

Data access abort exception, occurred pc update, and it also need to re-execute the exception that instruction, so pc = lr-8.

 

Through the above description, you can see the cause of single-chip interrupt return for many reasons, each method of response programs are not the same. ARM chip debugging process encountered in the interruption of the problem of friends may wish to carefully read this article, I believe will find a solution to the problem. You can also collect this article to prepare for contingencies, in the face of the wrong time to access.


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